[PATCH] D87384: [PowerPC] Add ISEL patterns for Mul with Imm.

[Jinsong Ji via Phabricator via llvm-commits]

jsji added a comment.

In D87384#2289477 <https://reviews.llvm.org/D87384#2289477>, @Esme wrote:

> Hi @jsji  An infinite loop will occur if we handle the scenario 1 ` (mul X, c2 << c1) ->  (mul (shl X, c1), c2)` in DAGCombiner, because there exists a reverse conversion `(mul (shl X, c1), c2) -> (mul X, c2 << c1)`.

Hmm.. then OK to keep this in ISEL, but please add comments about DAGcombiner prefer  (mul X, c2 << c1). Thanks


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