[PATCH] D87384: [PowerPC] Add ISEL patterns for Mul with Imm.

[Jinsong Ji via Phabricator via llvm-commits]

jsji added a comment.

I think we already have similar pattern for scenario 1 as well:

  // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
  // use.

Just that `(shl X,C)` is not constant there..

So I would assume dealing with similar situation controlled by `TLI.decomposeMulByConstant`will be easy and also no harm to other targets.
Targets can control add this scenario in their TLI if they also want this.

BTW: looks like x86 also has imul.

x86 also has `imul`



================
Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:4989
+    // If the shifted value fits 16 bits, we can transform the multiplication to
+    // "mulli + rldicr".
+    int64_t ImmSh = Imm >> Shift;
----------------
Maybe it would be clearer if we use DAG expression in comments. 
eg: `(mul X, c2 << c1) -> (rldicr (mulli X, c2 >> c1)  c1)`


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  https://reviews.llvm.org/D87384/new/

https://reviews.llvm.org/D87384