[PATCH] D88017: [AArch64] Enable Cortex-A55 schedmodel

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer updated this revision to Diff 293230.
SjoerdMeijer added a comment.

- pruned the test case, added comments for the different instruction categories to make the test more readable,
- fixed latencies for the FDIV and FSQRT instructions,
- regarding @evgeny777 's comment "WriteLD should be 3 cycles, not 4". I have kept it as it was, because in a first benchmark run I tried this regressed things a bit.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88017/new/

https://reviews.llvm.org/D88017

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s

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