[PATCH] D88017: [AArch64] Enable Cortex-A55 schedmodel

Mon Sep 21 07:41:16 PDT 2020

dmgreen added a comment.

Nice idea on how to write a test, even if it's not the cleanest thing I've ever seen.

It doesn't seem to have a lot of neon, but we can address that as we need to.

================
Comment at: llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s:1307
+dc	cisw, x30
+msr	TEECR32_EL1, x12
+msr	OSDTRRX_EL1, x12
----------------
Can you remove most of these msr/mrs's. We only need 1. Maybe same for dsb/dmb, they have little value in scheduling, usually.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D88017/new/

https://reviews.llvm.org/D88017