[PATCH] D87231: [AArch64] ExtractElement is free when combined with pairwise add

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

We had similar codegen matching problems for x86's horizontal ops and fixed them with DAGCombiner/ISel pattern matching. 
If you don't do that, then I think you're still going to miss faddp opportunities if the source/IR is already in the form with a shuffle.
Example:

  typedef float float2 __attribute__((ext_vector_type(2)));
  
  float faddp(float2 x) {
    return (__builtin_shufflevector(x, x, 1, 1) + x)[0];
  }



  $ clang -O1 faddp.c -S -o - -target aarch64 -mllvm -disable-vector-combine 
  faddp:                                  // @faddp
  	dup	v1.2s, v0.s[1]
  	fadd	v0.2s, v1.2s, v0.2s
  	ret


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https://reviews.llvm.org/D87231