[PATCH] D87231: [AArch64] ExtractElement is free when combined with pairwise add

[Sanne Wouda via Phabricator via llvm-commits]

sanwou01 added a comment.

Thanks @spatel . You're right that we miss that pattern, but, so does x86 currently it seems (I don't read x86 very well so I might be wrong). Using your faddp example:

  $  ./bin/clang -O1 ~/tmp/faddp.c -S -o - -target x86_64 -mllvm -disable-vector-combine
  ...
  faddp:                                  # @faddp
          .cfi_startproc
  # %bb.0:                                # %entry
          pushq   %rbp
          .cfi_def_cfa_offset 16
          .cfi_offset %rbp, -16
          movq    %rsp, %rbp
          .cfi_def_cfa_register %rbp
          movaps  %xmm0, %xmm1
          shufps  $85, %xmm0, %xmm1               # xmm1 = xmm1[1,1],xmm0[1,1]
          addss   %xmm0, %xmm1
          movaps  %xmm1, %xmm0
          popq    %rbp
          .cfi_def_cfa %rsp, 8
          retq

I did find `scalarizeBinOpOfSplats` in `DAGCombiner` but that doesn't seem to work here, nor do any of the other patterns in `SimplifyVBinOp`.

That said, it does seem to make sense to do this in DAGCombiner, thanks for the suggestion. I'll try that.


Repository:
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  https://reviews.llvm.org/D87231/new/

https://reviews.llvm.org/D87231