[PATCH] D86114: [SVE] Lower fixed length vXi8/vXi16 SDIV to scalable

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8945
+    // Convert vector of i8/i16 DIV to scalable to allow usual promotion.
+    return LowerToScalableOp(Op, DAG, /*OverrideNEON=*/true);
+  }
----------------
cameron.mcinally wrote:
> cameron.mcinally wrote:
> > paulwalker-arm wrote:
> > > I just wanted to double check that you are aware this is going to result in i8/i16 fixed length vector divides being different to the i32/i64 ones.  The latter being predicated with the former cases not (or rather using an "all true" predicate).
> > > 
> > > Given divides are rarely cheap I prefer the predicated route but I guess there's no reason to be consistent at this stage.
> > Oh, for the smaller vectors that are passed in regs? Yeah, I didn't catch that. Any clue why that's happening? Is it because there are no loads/stores to lower?
> Oh, I see what you're saying now. The second predicate register is being generated all1s. That's surprising. Ultimately, both the i32/i64 and i8/i16 cases should be going through `return LowerToPredicatedOp(Op, DAG, PredOpcode);`. I'll see if I can find the difference.
I see you're finding the answers quicker than I can type them :)

For what it's worth I've nothing against the current patch since it is simple and works, I just wanted to ensure you were aware what was going on.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D86114/new/

https://reviews.llvm.org/D86114