[PATCH] D84169: [Thumb] set code alignment for 16-bit load from constant pool

[Diogo N. Sampaio via Phabricator via llvm-commits]

dnsampaio added a comment.

Sorry, it seems I was looking the wrong instruction, it should be the label variant: `vldr.16 s0, .LCPI0_0`

So the correct instruction is: https://developer.arm.com/docs/ddi0597/h/simd-and-floating-point-instructions-alphabetic-order/vldr-literal-load-simdfp-register-literal

  For the half-precision scalar variant: the assembler calculates the required value of the offset from the Align(PC, 4) value of the instruction to this label. Permitted values are multiples of 2 in the range -510 to 510.


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  https://reviews.llvm.org/D84169/new/

https://reviews.llvm.org/D84169