[PATCH] D84169: [Thumb] set code alignment for 16-bit load from constant pool

[Diogo N. Sampaio via Phabricator via llvm-commits]

dnsampaio added a comment.

Hi, thanks for working on this.
What exactly are you trying to fix? From what I see from https://developer.arm.com/docs/ddi0597/h/simd-and-floating-point-instructions-alphabetic-order/vldr-immediate-load-simdfp-register-immediate
`VLDR.16  s0,{pc}+0x16` requires only a alignment of 2 bytes, as it has only a single zero appended in the case of half (.16):

  T1
  Half-precision scalar (size == 01)
  (Armv8.2)
  VLDR{<c>}{<q>}.16 <Sd>, [<Rn> {, #{+/-}<imm>}]
  esize = 8 << UInt(size);  add = (U == '1');
  imm32 = if esize == 16 then ZeroExtend(imm8:'0', 32) else ZeroExtend(imm8:'00', 32);


Repository:
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https://reviews.llvm.org/D84169