[PATCH] D84169: [Thumb] set code alignment for 16-bit load from constant pool

[Simon Wallis via Phabricator via llvm-commits]

simonwallis2 added a comment.

The significant phrase is the Align(PC, 4) part.
The calculated value of the offset depends on the alignment of the VLDR.16 instruction.
That is why the code section needs to be 4-byte aligned.
If the code section is 2-byte aligned and the linker places the section at a non-4-byte aligned address, the offset will point to a different address.


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  https://reviews.llvm.org/D84169/new/

https://reviews.llvm.org/D84169