[PATCH] D81172: [AMDGPU] Implement hardware bug workaround for image instructions

[Rodrigo Dominguez via Phabricator via llvm-commits]

rdomingu marked 2 inline comments as done.
rdomingu added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:3226-3228
+      // TODO Handle v3f16
+      if (StoreVT.getNumElements() == 3)
+        return Reg;
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arsenm wrote:
> There's no obstacle to handling v3 here, it should work in the other cases
Note that v3f16 is not handled in SIISelLowering.cpp either (line 7255). Are you suggesting we implement v3f16 there too?


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https://reviews.llvm.org/D81172