[PATCH] D81172: [AMDGPU] Implement hardware bug workaround for image instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp:3226-3228
+      // TODO Handle v3f16
+      if (StoreVT.getNumElements() == 3)
+        return Reg;
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rdomingu wrote:
> arsenm wrote:
> > There's no obstacle to handling v3 here, it should work in the other cases
> Note that v3f16 is not handled in SIISelLowering.cpp either (line 7255). Are you suggesting we implement v3f16 there too?
There is a v3f16 definition now, so you could. I think it's more important for globalisel to be more complete


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https://reviews.llvm.org/D81172