[PATCH] D83089: DomTree: Extract (mostly) read-only logic into type-erased base classes
Nicolai Hähnle via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 8 08:10:43 PDT 2020
nhaehnle added a comment.
In D83089#2134858 <https://reviews.llvm.org/D83089#2134858>, @kuhar wrote:
> This part of the code is *very* performance sensitive and definitely needs benchmarking before moving forward. Have you tried doing some performance evaluation on this change? I suggest compiling a few mid to large size programs (e.g., sqlite, webassembly, opt, clang, rippled) and compiling them into whole-program bitcode, and then running `opt -O3` on this bitcode. This is pretty easy with gllvm <https://github.com/SRI-CSL/gllvm>; I can dig up my old instruction if that would help.
I've done this now: used gllvm to extract bitcode of Z3, then run `perf stat opt -O3 z3.bc -o z3.out.bc`. 3 runs on both my branch and the underlying master:
Underlying master:
1.441.691.613.522 cycles:u # 3,948 GHz (83,34%)
1.511.470.542.186 instructions:u # 1,05 insn per cycle
1.445.040.063.358 cycles:u # 3,832 GHz (83,33%)
1.511.151.342.715 instructions:u # 1,05 insn per cycle
1.445.488.489.379 cycles:u # 3,851 GHz (83,34%)
1.510.528.339.517 instructions:u # 1,04 insn per cycle
My branch:
1.447.208.247.196 cycles:u # 3,920 GHz (83,33%)
1.506.361.797.982 instructions:u # 1,04 insn per cycle
1.451.415.961.317 cycles:u # 3,913 GHz (83,33%)
1.505.605.385.713 instructions:u # 1,04 insn per cycle
1.445.005.341.369 cycles:u # 3,908 GHz (83,33%)
1.506.364.033.713 instructions:u # 1,04 insn per cycle
So the results are a bit unintuitive: lower number of instructions overall on my branch, slightly higher average number of cycles.
Repository:
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CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83089/new/
https://reviews.llvm.org/D83089
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