[PATCH] D83137: [SVE][CodeGen] Legalisation of masked loads and stores
Kerry McLaughlin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 7 11:08:34 PDT 2020
kmclaughlin updated this revision to Diff 276145.
kmclaughlin added a comment.
Changes to IncrementMemoryAddress:
- Changed the assert added for scalable vectors to a report_fatal_error
- Replaced `Addr.getValueSizeInBits().getFixedSize()` with `AddrVT.getSizeInBits().getFixedSize()`
- Use `DataVT.getStoreSize()` instead of `DataVT.getSizeInBits()`
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D83137/new/
https://reviews.llvm.org/D83137
Files:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/test/CodeGen/AArch64/sve-split-load.ll
llvm/test/CodeGen/AArch64/sve-split-store.ll
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