[PATCH] D82520: [Power10] Implement Vector Splat Immediate Builtins in LLVM/Clang

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added a comment.

What I see from this patch is:

- builtins -> expressions
- intrinsics -> hw instructions.

I didn't see any test or something that we can prove that, the expression can be lowered to hw instructions.



================
Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:86
+vector signed int test_vec_vec_splati_si(void) {
+  // CHECK: ret <4 x i32>
+  return vec_splati(-1);
----------------
The test is too weak. Please check <4 x i32><i32 -1, i32 -1, i32 -1, i32 -1>


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:573
+let Predicates = [PrefixInstrs] in {
+  def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
+                                     (ins i32imm:$IMM32),
----------------
Not prefix instruction.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:581
+                                      [(set v2f64:$XT,
+                                        (PPCxxspltidp i32:$IMM32))]>;
+  def XXSPLTI32DX :
----------------
Can you explain more on why we need this pattern ? I didn't see any test for this .


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  https://reviews.llvm.org/D82520/new/

https://reviews.llvm.org/D82520