[PATCH] D81651: [AMDGPU][CODEGEN] Added support of new inline assembler constraints

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp marked 4 inline comments as done.
dp added inline comments.


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Comment at: llvm/docs/LangRef.rst:4151
+- ``J``: A 16-bit signed integer constant.
+- ``L``: A 15-bit unsigned integer constant.
 - ``A``: An integer or a floating-point inline constant.
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arsenm wrote:
> This one is weird; we don't actually have any of these instructions?
Sure, we do not have anything like this in AMDGPU ISA encodings and I'm not sure how useful this constraint would be. However we should probably support it for the sake of compatibility with GCC. 


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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:11065
+    unsigned UnusedBits = 64 - Size;
+    Val = (Val << UnusedBits) >> UnusedBits;
+  }
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arsenm wrote:
> Val & maskTrailingOnes(Size) might be clearer
Thanks! I was sure there is a function for this purpose in llvm libraries but was unable to find it. The name sounds a bit cryptic.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81651/new/

https://reviews.llvm.org/D81651