[PATCH] D81651: [AMDGPU][CODEGEN] Added support of new inline assembler constraints

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp updated this revision to Diff 272762.
dp marked 2 inline comments as done.
dp added a comment.

Summary of changes:

- simplified clearUnusedBits using maskTrailingOnes;
- fixed a bug in constraint identification (isImmConstraint).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81651/new/

https://reviews.llvm.org/D81651

Files:
  llvm/docs/LangRef.rst
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.h
  llvm/test/CodeGen/AMDGPU/inline-constraints.ll

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