[PATCH] D81511: [AArch64][SVE] Add legalization support for i32/i64 vector srem/urem

[Eli Friedman via Phabricator via llvm-commits]

efriedma marked 3 inline comments as done.
efriedma added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:213
   setOperationAction(ISD::FREM, VT, Expand);
+  setOperationAction(ISD::SDIVREM, VT, Expand);
+  setOperationAction(ISD::UDIVREM, VT, Expand);
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sdesmalen wrote:
> If you're adding these for ARM Neon and MVE, they should probably have tests similar to the one for SVE?
NEON and MVE don't have a vector divide instruction.  All this change does is make sure expandREM properly fails (so we continue calling UnrollVectorOp).

We have test coverage for this unrolling already.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81511/new/

https://reviews.llvm.org/D81511