[PATCH] D81511: [AArch64][SVE] Add legalization support for i32/i64 vector srem/urem

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

Nice improvement, LGTM!



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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp:1360
 }
+void VectorLegalizer::ExpandREM(SDNode *Node,
+                                SmallVectorImpl<SDValue> &Results) {
----------------
nit: missing whitespace above this line.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:213
   setOperationAction(ISD::FREM, VT, Expand);
+  setOperationAction(ISD::SDIVREM, VT, Expand);
+  setOperationAction(ISD::UDIVREM, VT, Expand);
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If you're adding these for ARM Neon and MVE, they should probably have tests similar to the one for SVE?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D81511/new/

https://reviews.llvm.org/D81511