[PATCH] D81139: [ARM] MVE VCVT lowering for f32->f16 truncs

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

In D81139#2073931 <https://reviews.llvm.org/D81139#2073931>, @efriedma wrote:

> > Due to v4f16 not being legal
>
> This is a MVE-specific thing? hmm.
>
> Dealing with mixed types is a recurring problem with target-independent vector handling; we should probably try to extend the approach currently used by SIGN_EXTEND_VECTOR_INREG to other cast opcodes, so we don't have to keep repeating exactly the same hacks for every target with vector registers.


Can you explain what kind of thing you are thinking of? A <4 x half> under MVE is very different to a <4 x i16> under MVE, as we currently do type promotion. And the "bottom half" of a v8i/f16 register is always a bit difficult to deal with.

If you have a better idea, I'm interested to hear it. I was currently planning to add something (probably pre-isel so it can look across BB boundaries) that took blobs of vector instructions surrounded by sext/zext/trunc (and now fpext/fptrunc) and turned them into something more MVE-y, by inserting shuffles like the tests above to allow us to use T/B instructions.

So I was thinking this was an MVE special.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81139/new/

https://reviews.llvm.org/D81139