[PATCH] D81139: [ARM] MVE VCVT lowering for f32->f16 truncs

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> Due to v4f16 not being legal

This is a MVE-specific thing? hmm.

Dealing with mixed types is a recurring problem with target-independent vector handling; we should probably try to extend the approach currently used by SIGN_EXTEND_VECTOR_INREG to other cast opcodes, so we don't have to keep repeating exactly the same hacks for every target with vector registers.


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https://reviews.llvm.org/D81139