[PATCH] D75751: [AArch64][SVE] Implement structured load intrinsics

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes updated this revision to Diff 266237.
c-rhodes edited the summary of this revision.
c-rhodes added a comment.

Changes:

- Rebased.
- Move lowering to DAGCombine pre-legalisation.
- Added assert for `VT.getVectorElementCount().Min % N == 0`.
- Removed `test/CodeGen/AArch64/sve-intrinsics-loads-with-extract.ll`.
- Added missing overloaded argument types to intrinsics in `test/CodeGen/AArch64/sve-intrinsics-loads.ll`.
- Removed `SubRegIdx` from `SelectPredicatedLoad` since `AArch64::zsub0` is always used.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75751/new/

https://reviews.llvm.org/D75751

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll

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