[PATCH] D80161: [CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias

[Jean-Michel Gorius via Phabricator via llvm-commits]

Kayjukh updated this revision to Diff 265561.
Kayjukh added a comment.
Herald added a subscriber: MatzeB.

Add some debug output to the instruction sheduler to signal wether or not a chain dependency has been added between two given instructions. This change allows us to properly test the effect of handling multiple memory operands in alias queries on instruction scheduling.

This update also adds a test case that makes use of the newly added scheduler debug output.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80161/new/

https://reviews.llvm.org/D80161

Files:
  llvm/lib/CodeGen/MachineInstr.cpp
  llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
  llvm/test/CodeGen/AArch64/merge-store-dependency.ll
  llvm/test/CodeGen/ARM/big-endian-neon-fp16-bitconv.ll
  llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
  llvm/test/CodeGen/Thumb2/mve-phireg.ll
  llvm/test/CodeGen/Thumb2/mve-vst3.ll
  llvm/test/CodeGen/Thumb2/umulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/X86/instr-sched-multiple-memops.mir
  llvm/test/CodeGen/X86/store_op_load_fold2.ll

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