[PATCH] D80161: [CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias

[Jean-Michel Gorius via Phabricator via llvm-commits]

Kayjukh added a comment.

In D80161#2044571 <https://reviews.llvm.org/D80161#2044571>, @efriedma wrote:

> On ARM specifically, operations don't usually more than one memoperand, with the exception of load store paired/multiple.  So yes, I can see it would be hard to trigger outside of scheduling.
>
> Maybe we could add some debug output to the scheduler showing when it does/does not add a dependency, and check that.  So it would be checking scheduling, but not the final schedule.


Following your suggestion, I added some debug output to the instruction scheduler. It makes it way easier to test the changes as we don't have to go through a rarely executed code path to see a change in the output.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80161/new/

https://reviews.llvm.org/D80161