[PATCH] D80161: [CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

On ARM specifically, operations don't usually more than one memoperand, with the exception of load store paired/multiple.  So yes, I can see it would be hard to trigger outside of scheduling.

Maybe we could add some debug output to the scheduler showing when it does/does not add a dependency, and check that.  So it would be checking scheduling, but not the final schedule.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80161/new/

https://reviews.llvm.org/D80161