[PATCH] D80161: [CodeGen] Add support for multiple memory operands in MachineInstr::mayAlias

[Jean-Michel Gorius via Phabricator via llvm-commits]

Kayjukh added a comment.

In D80161#2043591 <https://reviews.llvm.org/D80161#2043591>, @Kayjukh wrote:

> In D80161#2042626 <https://reviews.llvm.org/D80161#2042626>, @efriedma wrote:
>
> > I'd like to see an MIR test that shows the aliasing check actually working correctly.
>
>
> I will have to find something that fits in a test case and covers this case. Working on it!


@efriedma Except for some variations in instruction scheduling caused by the calls to `mayAlias` when adding chain dependencies, I cannot seem to find anything that could make for a good test case. I tried looking into the AArch64LoadStoreOptimizer as well as the ARMLoadStoreOptimizer but none of my attempts triggered the

  // FIXME: Need to handle multiple memory operands to support all targets.
  if (!hasOneMemOperand() || !Other.hasOneMemOperand())
    return true;

code path, even when compiling fairly complex codes for those targets.

Handcrafting a MIR test file that would trigger this code path proves to be quite challenging since we have no direct control over the propagation of memory operands. Did you have a specific test scenario in mind?


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