[PATCH] D79768: [ARM] Exclude LR from register classes in low overhead loops

[Sam Parker via Phabricator via llvm-commits]

samparker added a comment.

The added register pressure is a worry, but I don't see there's much we can do it about and I think it's a risk worth taking. Is it possible to add some MIR tests for the individual register classes?



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Comment at: llvm/lib/Target/ARM/ARMRegisterTypePass.cpp:100
+        TryConstrain(&ARM::rGPRRegClass, &ARM::rGPRnolrRegClass);
+        TryConstrain(&ARM::tGPREvenRegClass, &ARM::tGPREvennolrRegClass);
+
----------------
I think adding GPRwithZR and GPRwithZRnosp makes sense as well, especially since your test uses csinc.


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  https://reviews.llvm.org/D79768/new/

https://reviews.llvm.org/D79768