[PATCH] D79768: [ARM] Exclude LR from register classes in low overhead loops

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

This seems like an extremely big hammer to use just to ensure that the interval isn't split between the decrement and the end of the loop.  In particular, trying to list out all the possible register classes seems tricky.

I'd recommend investigating other approaches.  Maybe you could use an instruction bundle to force the instructions to stay adjacent?


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https://reviews.llvm.org/D79768