[PATCH] D79768: [ARM] Exclude LR from register classes in low overhead loops

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: samparker, SjoerdMeijer, efriedma, simon_tatham, ostannard.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, mgorny, qcolombet, MatzeB.
Herald added a project: LLVM.

In a low overhead loop, LR should ideally be used exclusively for the loop count, and not spilled and reloaded in the loop. This attempts to enforce that more directly by adjusting the register classes of registers used or def'd in the loop to no include LR. This can help especially to prevent the live range or LR from being being split between t2LoopDec and t2LoopEnd, meaning we revert the loop less often (and don't end up with movs at the same time!)

It does mean that we have a register less, which can mean we end up spilling other register more. On average this should be an improvement though.


https://reviews.llvm.org/D79768

Files:
  llvm/lib/Target/ARM/ARM.h
  llvm/lib/Target/ARM/ARMRegisterInfo.td
  llvm/lib/Target/ARM/ARMRegisterTypePass.cpp
  llvm/lib/Target/ARM/ARMTargetMachine.cpp
  llvm/lib/Target/ARM/CMakeLists.txt
  llvm/test/CodeGen/ARM/O3-pipeline.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/regalloc.ll
  llvm/test/CodeGen/Thumb2/high-reg-spill.mir
  llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll

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