[PATCH] D78272: [PowerPC] DAG Combine to transform shifts into multiply-high

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15905
+                               RightOp.getOperand(0));
+  return (IsSignExt ? DAG.getSExtOrTrunc(Result, DL, WideVT1)
+                    : DAG.getZExtOrTrunc(Result, DL, WideVT1));
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I think what extend to use at the end needs to be base of the shift opcode not the extend opcode. If its an SRL, you need to put 0s in the upper bits even if the multiply is MULHS.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78272/new/

https://reviews.llvm.org/D78272