[PATCH] D78272: [PowerPC] DAG Combine to transform shifts into multiply-high

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 6 11:52:47 PDT 2020


craig.topper added a comment.

In D78272#2022341 <https://reviews.llvm.org/D78272#2022341>, @RKSimon wrote:

> In D78272#2021795 <https://reviews.llvm.org/D78272#2021795>, @amyk wrote:
>
> > In D78272#1997042 <https://reviews.llvm.org/D78272#1997042>, @RKSimon wrote:
> >
> > > Is there anything that would stop us making this a generic combine in DAGCombiner?
> >
> >
> > Is there a preference to have this target independent instead? It may be possible if there is a preference/demand for it to be.
>
>
> @craig.topper - any thoughts? Given how expensive PMULLD/PMULLQ can be, we don't much to encourage PMULH generation.


We have a combine similar to this in X86 back it starts at the truncate not the shift.



================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15882
+  unsigned NarrowVTSize = NarrowVT.getScalarSizeInBits();
+  if (WideVT1.getScalarSizeInBits() != 2 * NarrowVTSize)
+    return SDValue();
----------------
SIGN_EXTEND_INREG will never pass this check will it? The input and output type for that are the same. There's an extra operand carrying the type to extend from.


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