[PATCH] D78137: [RegBankSelect] Hide assertion failure from LLT::getScalarSizeInBits

Vedant Kumar via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 14 16:20:34 PDT 2020


vsk added a comment.

I'm also not sure how to explain why this assert doesn't fire as often in practice. In this test case, we hit the failure while processing the function 'phiPropagation'. It looks like we take the getInstrMappingImpl path for the first instruction in the entry block (LDRWui), but that that does not set the LLT for %0:gpr32? That would explain what happens next: we subsequently take the generic path for the DBG_VALUE and hit the assert. FWIW this assertion fires on quite a few AArch64 .mir tests, not just this one. So there's some discrepancy here we don't fully understand.

Here is my debug session with this patch backed out:

  frame #8: 0x00000001022bb012 llc`llvm::RegBankSelect::runOnMachineFunction(this=0x000000010572e670, MF=0x00000001057745a0) at RegBankSelect.cpp:700:12 [opt]
     697        // if (MI.isDebugInstr())
     698        //   continue;
     699
  -> 700        if (!assignInstr(MI)) {
     701          reportGISelFailure(MF, *TPC, *MORE, "gisel-regbankselect",
     702                             "unable to map instruction", MI);
     703          return false;
  (lldb) p MI.dump()
    DBG_VALUE %0:gpr32, $noreg, !"1", !DIExpression(), debug-location !23; /Users/vsk/src/llvm-project-master/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir:6:1 line no:6
  (lldb) p MF.dump()
  # Machine code for function phiPropagation: IsSSA, TracksLiveness, Legalized
  
  bb.0.entry:
    successors: %bb.2(0x40000000), %bb.1(0x40000000); %bb.2(50.00%), %bb.1(50.00%)
    liveins: $x0, $x1, $w2
    %0:gpr32 = LDRWui killed $x0, 0, debug-location !23 :: (load 4 from %ir.src); /Users/vsk/src/llvm-project-master/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir:6:1
    DBG_VALUE %0:gpr32, $noreg, !"1", !DIExpression(), debug-location !23; /Users/vsk/src/llvm-project-master/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir:6:1 line no:6


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