[PATCH] D77631: [SelectionDAG] Make getZeroExtendInReg take a vector VT if the operand VT is a vector.

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

Being consistent with SIGN_EXTEND_INREG is a good argument.  LGTM with clang-format issues fixed.



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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:3536
     SDValue CarryExt =
-        DAG.getZeroExtendInReg(DAG.getZExtOrTrunc(Carry, dl, VT), dl, MVT::i1);
+        DAG.getNode(ISD::AND, dl, VT, DAG.getZExtOrTrunc(Carry, dl, VT), One);
     SDValue Sum2 = DAG.getNode(Op, dl, VT, Sum, CarryExt);
----------------
I'm a little surprised you decided to remove the call to getZeroExtendInReg here.  I guess it makes sense when the type you're extending from doesn't naturally exist otherwise.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77631/new/

https://reviews.llvm.org/D77631