[PATCH] D77631: [SelectionDAG] Make getZeroExtendInReg take a vector VT if the operand VT is a vector.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc41685b16fcc: [SelectionDAG] Make getZeroExtendInReg take a vector VT if the operand VT is a… (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D77631?vs=255600&id=255762#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77631/new/

https://reviews.llvm.org/D77631

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp

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