[PATCH] D77631: [SelectionDAG] Make getZeroExtendInReg take a vector VT if the operand VT is a vector.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 6 23:57:45 PDT 2020
craig.topper created this revision.
craig.topper added reviewers: RKSimon, efriedma, spatel.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.
This removes a call to getScalarType from a bunch of call sites.
It also makes the behavior consistent with SIGN_EXTEND_INREG.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D77631
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
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