[PATCH] D76201: [TargetLowering] Only demand a rotation's modulo amount bits

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: dylanmckay, aykevl, rsandifo, uweigand, hfinkel, craig.topper.
Herald added subscribers: Jim, hiraditya, nemanjai.
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RKSimon marked 2 inline comments as done.
RKSimon added inline comments.
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Comment at: llvm/test/CodeGen/SystemZ/rot-01.ll:30
 ; CHECK-NEXT:    br %r14
   %mod = urem i64 %amt, 32
 
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@uweigand Should this be 32 or 64?


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Comment at: llvm/test/CodeGen/SystemZ/rot-02.ll:7
 
 ; Test that AND is not removed when some lower 6 bits are not set.
 define i32 @f1(i32 %val, i32 %amt) {
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@uweigand This comment doesn't seem to match the test - any suggestions?


ISD::ROTL/ROTR rotation values are guaranteed to act as a modulo amount, so for power-of-2 bitwidths we only need the lowest bits.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76201

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
  llvm/test/CodeGen/AVR/rot.ll
  llvm/test/CodeGen/PowerPC/rotl-2.ll
  llvm/test/CodeGen/SystemZ/rot-01.ll
  llvm/test/CodeGen/SystemZ/rot-02.ll
  llvm/test/CodeGen/SystemZ/shift-04.ll
  llvm/test/CodeGen/SystemZ/shift-08.ll
  llvm/test/CodeGen/Thumb2/thumb2-ror.ll
  llvm/test/CodeGen/X86/combine-rotates.ll
  llvm/test/CodeGen/X86/vector-fshl-rot-512.ll
  llvm/test/CodeGen/X86/vector-fshr-rot-512.ll

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