[PATCH] D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions

[Simon Cook via Phabricator via llvm-commits]

simoncook added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp:15
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "RISCVSubtarget.h"
 #include "llvm/CodeGen/GlobalISel/RegisterBank.h"
----------------
This looks strange this way round, does this still build if you swap lines 14 and 15?


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Comment at: llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp:98
+  // Indicate if LLT sizes don't match available register banks.
+  // TODO: Fixed size FPR reigsters on both Rv32/RV64.
+  for (const auto &Op : MI.operands()) {
----------------
reigsters -> registers, nitpick: RV32


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76051/new/

https://reviews.llvm.org/D76051