[PATCH] D76052: [X86] Disable nop padding before instruction following a prefix

[Kan Shengchen via Phabricator via llvm-commits]

skan created this revision.
skan added reviewers: reames, MaskRay, craig.topper, LuoYuanke, jyknight.
Herald added a subscriber: hiraditya.
Herald added a project: LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76052

Files:
  llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
  llvm/test/MC/X86/align-branch-64-prefix.s


Index: llvm/test/MC/X86/align-branch-64-prefix.s
===================================================================
--- /dev/null
+++ llvm/test/MC/X86/align-branch-64-prefix.s
@@ -0,0 +1,76 @@
+  # RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu --x86-align-branch-boundary=32 --x86-align-branch=jmp+call %s | llvm-objdump -d --no-show-raw-insn - | FileCheck %s
+
+  # Exercise cases where prefixes are specified for instructions to be aligned
+  # and thus can't add a nop in between without changing semantic.
+
+  .text
+
+  # CHECK: 1d:       int3
+  # CHECK: 1e:       jmp
+  # CHECK: 24:       int3
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  CS
+  jmp baz
+  int3
+
+  # CHECK: 5d:       int3
+  # CHECK: 5e:       jmp
+  # CHECK: 64:       int3
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  GS
+  jmp baz
+  int3
+
+  # CHECK: 9d:       int3
+  # CHECK: 9e:       call
+  # CHECK: a6:       int3
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  data16
+  call *___tls_get_addr at GOT(%ecx)
+  int3
+
+  # CHECK: de:       lock
+  # CHECK: df:       jmp
+  # CHECK: e4:       int3
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  lock
+  jmp baz
+  int3
+
+  # CHECK: 11d:       int3
+  # CHECK: 11e:       jmp
+  # CHECK: 124:       int3
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  rex64
+  jmp baz
+  int3
+
+  # CHECK: 15d:      int3
+  # CHECK: 15e:      {{.*}} jmp
+  # CHECK: 164:      int3
+  .p2align  5
+  .rept 30
+  int3
+  .endr
+  xacquire
+  jmp baz
+  int3
+
+  .section ".text.other"
+bar:
+  retq
Index: llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
===================================================================
--- llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
+++ llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
@@ -505,6 +505,11 @@
     // instruction delay, inserting a nop would change behavior.
     return;
 
+  if (X86II::isPrefix(MCII->get(PrevInst.getOpcode()).TSFlags))
+    // If this instruction follows a prefix, inserting a nop would change
+    // semantic.
+    return;
+
   if (!isMacroFused(PrevInst, Inst))
     // Macro fusion doesn't happen indeed, clear the pending.
     PendingBoundaryAlign = nullptr;


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