[PATCH] D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill created this revision.
lewis-revill added reviewers: asb, lenary, luismarques, simoncook, apazos, weiwei, shiva0217.
Herald added subscribers: llvm-commits, evandro, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, kito-cheng, niosHD, sabuasal, johnrusso, rbar, hiraditya, rovka.
Herald added a project: LLVM.
lewis-revill added a parent revision: D76007: [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes.

This patch implements the getInstrMapping hook for RISCVRegisterBankInfo and others in order to correctly select the GPR register bank for operands of ALU instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76051

Files:
  llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu64.mir

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