[PATCH] D76023: [ARM] Sink splats to vector float instructions

[Sam Parker via Phabricator via llvm-commits]

samparker added a comment.

Annoying about the vmovs.... I can't see, with register aliasing, how this codegen wouldn't be a regression.



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Comment at: llvm/test/CodeGen/Thumb2/mve-floatregloops.ll:644
+; CHECK-NEXT:    vldrw.u32 q3, [r0], #16
+; CHECK-NEXT:    vdup.32 q1, r12
+; CHECK-NEXT:    vneg.f32 q2, q2
----------------
So why has this caused the vdup to not be hoisted anymore?


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  https://reviews.llvm.org/D76023/new/

https://reviews.llvm.org/D76023