[PATCH] D76023: [ARM] Sink splats to vector float instructions

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: SjoerdMeijer, simon_tatham, samparker, ostannard.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: LLVM.

Some MVE floating point instruction have gpr register variants that take the scalar gpr value and splat them to all lanes. In order to accept them in loops, the shuffle_vector and insert need to be sunk down into the loop, next to the instruction so that ISel can see the whole pattern.

This does that sinking for FAdd, FSub, FMul and FCmp. The patterns for mul are slightly more constrained as there are no fms variants taking register arguments.

This on it's own can leave extra MOV instructions in the loops as they are not pulled out by MachineLICM. This will be addressed in a followup.


https://reviews.llvm.org/D76023

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/Thumb2/mve-floatregloops.ll
  llvm/test/CodeGen/Thumb2/mve-pred-threshold.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D76023.249738.patch
Type: text/x-patch
Size: 20196 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200311/47a5293b/attachment.bin>