[PATCH] D76023: [ARM] Sink splats to vector float instructions

Thu Mar 12 07:35:55 PDT 2020

dmgreen marked an inline comment as done.
dmgreen added a comment.

In D76023#1918962 <https://reviews.llvm.org/D76023#1918962>, @samparker wrote:

> Annoying about the vmovs.... I can't see, with register aliasing, how this codegen wouldn't be a regression.

Certainly would be on it's own, but people will be writing similar code with intrinsics anyway so is something we need to get sorted. The second part is in D76024 <https://reviews.llvm.org/D76024> if you didn't already see it. Plan is to commit them together, but I needed the tests from here to test that patch.

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Comment at: llvm/test/CodeGen/Thumb2/mve-floatregloops.ll:644
+; CHECK-NEXT:    vldrw.u32 q3, [r0], #16
+; CHECK-NEXT:    vdup.32 q1, r12
+; CHECK-NEXT:    vneg.f32 q2, q2
----------------
samparker wrote:
> So why has this caused the vdup to not be hoisted anymore?
The vdup depends on the vmov and the vmov isn't hoisted.

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https://reviews.llvm.org/D76023