[PATCH] D75371: [ARM] Optimise ASRL/LSRL to smaller shifts using demand bits.

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:14124
+          if (N->getOpcode() == ARMISD::ASRL) {
+            SDValue NewShift = DAG.getNode(ISD::SRA, DL, MVT::i32, Op1,
+                                          DAG.getConstant(31, DL, MVT::i32));
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For readability, maybe introduce a lambda to help create the shift and do the replacement? Some aptly named variables for shift ranges and whether we're doing a logical/left/right shift could also help.


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  https://reviews.llvm.org/D75371/new/

https://reviews.llvm.org/D75371