[PATCH] D75371: [ARM] Optimise ASRL/LSRL to smaller shifts using demand bits.

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 248256.
dmgreen added a comment.

Rebase to on top of D75553 <https://reviews.llvm.org/D75553> (I had not really considered them together when I wrote that, only from the times we would generate the nodes from shifts. From intrinsics more cases can come up). It makes sense to do that one first as this has become more complex.

I have tried to add a few of the obvious cases that I thought might come up, when parts of the shift are not used. The intrinsics are really designed for variable shifts but they can become constant during optimisation (and the first example I saw of someone using them was asrl(X, 23), as opposed to using a standard shift).

This doesn't feel like the prettiest code I've ever written. Suggestions welcome.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75371/new/

https://reviews.llvm.org/D75371

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/test/CodeGen/Thumb2/fir.ll
  llvm/test/CodeGen/Thumb2/mve-intrinsics/longshift-demand.ll
  llvm/test/CodeGen/Thumb2/shift_parts.ll

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