[PATCH] D72799: [SVE] Add SVE2 patterns for unpredicated multiply instructions

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr marked 2 inline comments as done.
dancgr added a comment.

In D72799#1822588 <https://reviews.llvm.org/D72799#1822588>, @efriedma wrote:

> Can we also also add mul patterns for targets that have SVE, but not SVE2?


That instruction is restricted to SVE2. Do we have unpredicated vector mul instructions for SVE targets as well?

The way the instruction is implemented did not allow me to match with SVE targets.



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Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1192
+
+def int_aarch64_sve_mul_z      : AdvSIMD_Pred2VectorArg_Intrinsic;
+def int_aarch64_sve_smulh_z    : AdvSIMD_Pred2VectorArg_Intrinsic;
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efriedma wrote:
> This name seems strange.  Why "z"?
I just followed the name similar to the one for logical predicated instructions. I'm not sure if that is the correct way to name predicated intrinsics. I marked the place with a comment.


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Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1555
 
 def int_aarch64_sve_and_z   : AdvSIMD_Pred2VectorArg_Intrinsic;
 def int_aarch64_sve_bic_z   : AdvSIMD_Pred2VectorArg_Intrinsic;
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@efriedma Here!


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  https://reviews.llvm.org/D72799/new/

https://reviews.llvm.org/D72799