[PATCH] D72799: [SVE] Add SVE2 patterns for unpredicated multiply instructions

Wed Jan 15 13:30:42 PST 2020

efriedma added a comment.

In D72799#1822599 <https://reviews.llvm.org/D72799#1822599>, @dancgr wrote:

> In D72799#1822588 <https://reviews.llvm.org/D72799#1822588>, @efriedma wrote:
>
> > Can we also also add mul patterns for targets that have SVE, but not SVE2?
>
>
> That instruction is restricted to SVE2. Do we have unpredicated vector mul instructions for SVE targets as well?

We can synthesize a predicate using ptrue.  We do this in a few places currently; for example, to implement bswap.

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Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1555

 def int_aarch64_sve_and_z   : AdvSIMD_Pred2VectorArg_Intrinsic;
 def int_aarch64_sve_bic_z   : AdvSIMD_Pred2VectorArg_Intrinsic;
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dancgr wrote:
> @efriedma Here!
I think here the "_z" is meant to indicate that the predicate operand is "<Pg>/Z".

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  https://reviews.llvm.org/D72799/new/

https://reviews.llvm.org/D72799