[PATCH] D71917: Optimization of inserting vxi1 sub vector into vXi1 vector

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:5913
+  
+    // Reduce to original width if needed.
+    return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx);
----------------
RKSimon wrote:
> "if needed" ?
That comment is taken from the end of the function. WideOpVT and OpVT might be the same. There’s a check for that case in getNode that will just return the input vector in that case.


Repository:
  rL LLVM

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  https://reviews.llvm.org/D71917/new/

https://reviews.llvm.org/D71917