[PATCH] D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr added a comment.

In D71779#1795054 <https://reviews.llvm.org/D71779#1795054>, @efriedma wrote:

> Wong SMAX; you're referring to VECREDUCE_SMAX, which isn't relevant here.  There is no IR intrinsic for ISD::SMAX; it's pattern-matched from select instructions.


That makes way more sense, I have updated the patch to reflect that.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D71779/new/

https://reviews.llvm.org/D71779