[PATCH] D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Wong SMAX; you're referring to VECREDUCE_SMAX, which isn't relevant here.  There is no IR intrinsic for ISD::SMAX; it's pattern-matched from select instructions.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D71779/new/

https://reviews.llvm.org/D71779