[PATCH] D71779: [AArch64][SVE] Add patterns for signed and unsigned min/max instructions

[Danilo Carvalho Grael via Phabricator via llvm-commits]

dancgr marked an inline comment as done.
dancgr added a comment.

As far as I know the ISD::SMAX only takes one input (https://llvm.org/docs/LangRef.html#llvm-experimental-vector-reduce-smax-intrinsic), in this case we need two inputs so we can do the max between the input vector and the immediate value.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:2944
   if (auto CNode = dyn_cast<ConstantSDNode>(N)) {
-    uint64_t ImmVal = CNode->getZExtValue();
+    int64_t ImmVal = CNode->getZExtValue();
     SDLoc DL(N);
----------------
This shouldn't be here.


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  https://reviews.llvm.org/D71779/new/

https://reviews.llvm.org/D71779